In digital electronic systems where components can be substituted with differing components, there is a need to ensure that differing components will function correctly when connected. In many computer systems, there are a number of widely accepted or “standardized” interfaces or busses with widely used or standardized connectors to provide a point where differing components can be connected. Those who manufacture the differing components expect to be able to design their components to connect at that point and have those components work correctly.
Specifically, in the area of so-called “personal” computers, there are a number of standardized interfaces by which such components as a processor are attached to other components, e.g., “socket 7,” “slot 1,” “socket 370,” “slot 2” and “socket 478,” just to name a few. Similarly, a number of standardized interfaces exist by which other components, such as I/O cards for personal computers, can be connected, e.g., “ISA,” “EISA,” “PCI,” “AGP” and “PCI-X.”
A number of such interfaces have spawned multiple variants where one of the differentiating features is the clock speed at which addresses, data and/or other signals are transferred. By way of example, what is commonly referred to as the “socket 7” interface is available with variations in which the clock speed can be 50, 60, 66, 75 or 100 MHz. Similarly, the “PCI” interface is available in variations with a 25, 30, 33 or 66 MHz clock.
Furthermore, it is common practice to design components that work with such interfaces to use an internal clock with a speed derived from the clock speed of such an interface. Such a derived clock may operate at a fraction of the clock speed of such an interface or may operate at a multiple of the clock speed of such an interface.
Difficulties arise when two components are connected by such an interface where one of the two components is able to function with that interface having a higher clock speed than the other component. It is commonly left to those who assemble such components together to determine the minimum and maximum clock speeds at which the interface of each component can be operated, and to choose a common clock speed that will enable all of the components to work together. It is also commonly left to those who assemble such components together to determine the minimum and maximum clock speed of the internal clock of at least one of the components, and to choose a ratio between the common clock speed chosen for interface and the internal clock speed of that component.
Therefore, the success in assembling such components together depends, to some degree, on those who do the assembly work in determining minimum and maximum clock speeds and in choosing workable clock speeds and ratios of clock speeds. Errors made in determining minimum and maximum clocks speeds or in choosing workable clock speeds and ratios can result in components not working correctly together, and/or components being damaged. A need exists to provide a way to assemble such components that eliminates the opportunity for such errors to be made.